To ensure proper functionality and reliability, manufacturers typically test SOC integrated circuits (ICs) before shipping SOC ICs to customers. One system commonly employed to test SOC ICs is the Agilent 93000 SOC Tester, which supports concurrent tests. Portions of the Agilent 93000 SOC Tester are described in U.S. Pat. No. 6,756,778 to Hirschmann entitled “Measuring and/or calibrating a Test Head;” U.S. Pat. No. 5,558,541 to Botka et al. entitled “Blind Mate Connector for an Electronic Circuit Tester;” and U.S. Pat. No. 5,552,701 to Veteran et al. entitled “Docking System for an Electronic Circuit Tester.”
As illustrated in FIG. 1, the Agilent 93000 Tester 100 comprises test head 110 with DUT (Device under test) interface 120, manipulator 130 for positioning test head 110, DUT board 150 which plugs into underlying DUT interface 120, support rack 140 for supplying test head 110 with electrical power, cooling water and compressed air (not shown in the Figures) and a computer workstation (not shown in the Figures) which serves as the user interface to Tester 100.
Test head 110 is an important component in the system and comprises tester electronics and additional analog modules. Test head 110 may be configured with 512 pins or 1024 pins. The 512 pin test head supports 4 card cages while the 1024 pin test head supports 8 card cages. Each card cage can contain 8 digital boards or 8 analog modules, respectively. A single board has 16 pins, making 128 pins per cage. Therefore, the 4-cage test head contains 512 pins and the 8-cage test head 1024 pins. The DUT is mounted on DUT board 150, which is connected to the I/O channels by DUT interface 120. DUT interface 120 consists of high performance coax cabling and spring contact pins (pogo pins) which establish electrical connection with DUT board 120.
DUT interface 120 provides docking capabilities to handlers and wafer probers. The docking mechanism is controlled by compressed air (not shown in the Figures), and if required may also be operated manually. Test head 110 is water-cooled and receives its cooling water supply from support rack 140, which in turn is connected by two flexible hoses to the cooling unit (not shown in the Figures).
General-purpose manipulator 130 supports and positions test head 110. Manipulator 130 provides 6 degrees of freedom for precise and repeatable connections between test head 100 and handlers or wafer probers.
Support rack 140 is attached to manipulator 130 and serves as the interface between test head 110 and AC power, cooling water and compressed air. Tester 100 may also comprise additional support racks such as analog support racks for installing additional analog instruments.
An HP-UX workstation (not shown in the Figures) may serve as the interface between the user and tester 100. At the present time, Agilent 93000 SOC Series SmarTest software runs on the HP-UX workstation under the HP-UX operating system, although other suitable operating systems such as Linux or other workstations may certainly be used. SmarTest allows setups and test data to be downloaded to the test system, and further permits editing of such information. All testing is carried out in the test system. Results are read back by the workstation and displayed on the monitor. During test program execution, upload and download are typically not required since the test processors act independently from the workstation once the test program has begun running.
On the workstation, a diagnostic program can be run to check the system periodically or to identify the source of a problem. Configuration of Tester 100 involves assigning digital channel boards, power supplies, and analog instruments to specific channels of the test head and providing for associated mainframe components (such as an alternate master clock (AMC)) external to the test head.
Test head electronics components supply power to the various DUTs and perform measurements. Some test head functions and key elements are as follows:    DC/DC conversion and distribution of supply voltages    Interfacing via fiber optical cable to the workstation    Internal communication via data bus, address bus, and control bus    Communication clock generation and distribution    Master clock generation and distribution    High precision parametric measurement unit (HPPMU)    Interfacing to external clock    Supplying power to the DUT    Making channel measurements
Each pin in the platform provides period, timing, levels, patterns and sequencing, enabling each tester pin to independently operate in any number of different modes. Instead of sharing testing resources, every pin supports a full range of tester modes including clock, SCAN, BIST-control, functional, APG, and digital source and capture.
Such flexibility in Tester 100 allows for on-the-fly grouping of pins into virtual ports to test target IP blocks. As a result, the platform is capable of testing multiple blocks concurrently. Once a test has been completed, tester pins may be immediately reconfigured and assembled into new port configurations to conduct a completely different set of tests.
The architecture of Tester 100 provides support for concurrent tests on potentially dozens of ports with different sequencing and digital data rates. The test-processor-per-pin architecture of Tester 100 allows it to function as a scalable platform. Tester 100 supports test technologies that include RF, analog, digital and mixed signal, each fully capable of being used concurrently.
FIG. 2 illustrates the placing of DUT 160 on packaged parts DUT board 150, and the positioning of DUT board 150 above test head 110.
As shown in FIG. 3, instead of employing packaged parts DUT board 150 of FIG. 2, where DUT 160 is placed directly on DUT board 150, wafer prober DUT board 155 is placed on top of DUT interface 120. Several further components are then stacked atop wafer prober DUT board 155: pogo tower 165, probe card 180 and wafer 190. DUT board 155, stiffener assembly 170 and pogo tower 165 together form a Wafer Prober Interface (WPI), which is made in two sizes: a 9.5″ WPI and a 12″ WPI. A WPI DUT board (small or large, corresponding to 512 or 1024 pins) connects the pogo pins of the test head electronics to the pogo pins of pogo tower 165. It also maps the rectangular pogo pin layout of the test head to the circular contact layout of the pogo tower probe card. A standard DUT board provided by Agilent contains an EEPROM that identifies the board. Customized WPI DUT boards may have different pin mapping, connect several pins, or provide relays and filter circuits.
System-on-a-chip ICs that are to be tested on Tester 100 are loaded one-by-one into test head 110, or one-by-one into DUT board 150 inserted into test head 110. Electronic tests are then performed on each of the SOC ICs, after the completion of which the SOC ICs are removed one-by-one from test head 110 or DUT board 150 plugged into test head 110. While SOC ICs are being inserted into or removed from test head 110 or DUT board 150, no electronic testing of ICs occurs.
It will now be seen that reducing the amount of time required per DUT to load and unload DUTS into or from test head 110 or DUT board 150 will result in a reduction of the amount of time, and therefore the cost required, to test SOC ICs. What is needed is an SOC IC electronic circuit tester requiring less time to test SOC ICs, and to load and unload same from test head 110 or DUT board 150.